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SCAD241018 - Physical Verification Cad, Engineer

Post an ad like this for FREE!
  • Date Listed 24/10/2018
  • Job Type Full-Time
  • EA License Number 91C2918
  • Company Website http://www.adecco.com.sg/
  • Company Name Adecco - GS
  • Education Level Diploma
Our client is a Semiconductor MNC company and is looking for talent to join their organization in Singapore!

Job Description

* Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
* Co-work with Place & Route team to resolve full-chip layout integration issues.
* Coordinates with internal IP owners on IP related issues.
* Coordinates with Manufacturing Team on DRC related issues.
* Provide automation solutions to improve efficiency in tape-out flow.
* Report on tapeout issues.
* Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
* Develop layout implementation flow and physical verification flow
* Co-work with QA team to reduce the PDKs/Rule deck defects
* Implement automation scripts in C-shell and Perl

Job Requirements

* Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
* Familiar with IC Design front-to-backend flow
* Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
* Proficient in script programming, such as, Tcl, Perl or C-shell
* Proficient in UNIX (Linux) platforms
* Strong communication skills, problem solving and analytical skill

Next step

* Prepare your updated resume (please include your current salary package with full breakdown such as base, incentives, annual wage supplement, etc.) and expected package.
* Simply click on 'Apply here' to drop your resume.
* All shortlisted candidates will be contacted.

Jolinda Yow Jia Min
Direct Line: 6697 7782
EA License No: 91C2918
Personnel Registration Number: R1654296

*** Clike here to apply.
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